Schaltung um redundante Daten einer Redundanzschaltung innerhalb einer Speicheranordnung durch zeitgeteilte Annäherung zu übertragen

Circuit pour transférer des données de redondance dans un circuit à redondance à l'intérieur d'un circuit de mémoire par une approche en temps partagé

Circuit for transferring redundancy data of a redundancy circuit inside a memory device by means of a time-shared approach

Abstract

In a memory device equipped with a redundancy circuit comprising at least one redundancy memory register (RR1-RRn) storing a defective address of a defective memory element and an identifying code (OC0-OC3) suitable for identifying a portion of a matrix of memory elements wherein the defective memory element is located, a circuit for transferring redundancy data of a redundancy circuit inside the memory device is provided. The circuit comprises a shared bus (INTBUS) of signal lines (INTBUSm) provided in the memory device to interconnect a plurality of circuit blocks (100,101,8) of the memory device and for transferring signals between the circuit blocks. The shared bus (INTBUS) can be selectively to the various circuit blocks, and a bus assignment circuit (4,7) associated to the redundancy circuit is provided for assigning, during a prescribed time interval of a read cycle of the memory device, the shared bus (INTBUS) to the redundancy circuit whereby in the prescribed time interval the identifying code (OC0-OC3) stored in the redundancy memory register can be transferred onto the shared bus (INTBUS).

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Patent Citations (3)

    Publication numberPublication dateAssigneeTitle
    EP-0668562-A1August 23, 1995SGS-THOMSON MICROELECTRONICS S.r.l.Procédé de programmation de registres de redondance dans un circuit intégré à redondance de colonne pour dispositif de mémoire à semi-conducteur
    US-4495603-AJanuary 22, 1985Varshney Ramesh CTest system for segmented memory
    US-4628480-ADecember 09, 1986United Technologies Automotive, Inc.Arrangement for optimized utilization of I/O pins

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